Why are Registers important?
These days Software addressable registers are present in large numbers in a SoC and IP. For instance, a typical VGA/LCD controller contains 560 registers, a larger design such as a microprocessor like UltraSparc contains thousands of registers. Registers need to be specified, designed, verified, validated, and debugged. All these activities add up to consume a significant amount of time estimated to be about 25% of the entire development effort.
Fortunately, the industry can come together to solve the problem of register verification. The Verification IP technical (VIP-TC) committee under the auspices of Accellera has recently come up with the Universal Verification methodology – UVM library based on collaborative work between the big 3 EDA companies – Mentor, Synopsys and Cadence along with big customer companies such as Freescale, AMD, Cisco, Intel, etc. and smaller services companies.
The VIP-TC has included a register package in UVM that enables users to create a “shadow model” of the hardware’s register and memory map. This UVM register package contains classes for registers, register fields, register files, memories, blocks etc. This enables users to create the hardware register model.
UVM register is a base class library –
– Don’t have to write it yourself- like C/C++ libraries.
– Raise abstraction level
Use register names instead of addresses�Ц
– write (“dut.t1.register1”, data)
Equally important is the set of classes that help in automatically verifying the register model based on its specified properties.
What parameters should be looked at when selecting an automatic register generation methodology.
1. Buy Vs. build your own. If you do decide to build your own, remember the standards keep evolving and you would constantly need to update the generator.
2. Where are the register definitions located? Possible locations are :
Word, Excel, ASCII text files.
3. What outputs besides UVM need to be generated?
Users may have legacy environments such as OVM, VMM, or it may now be required to generate IP-XACT. RTL and C/C++ class files for firmware may also be required.
4. Verification team’s comfort factor in using a vendor tool that makes them re-enter the register spec in its special language or GUI.
IDesignSpec provides the most thorough and complete set of functionality in register management. Engineers don’t need to spend countless hours chasing register bits through the design, verification and validation process. Instead, they describe the register map once and for all, in a document, and that is considered “golden”. All files required by downstream processes are generated from that single source. This improves the engineers’ productivity and quality of results.
With IDesignSpec, users can describe the entire register map right in their document. This “live” document automatically generates classes and structures compliant with UVM register package. Other outputs such as RTL, C/C++ headers, IP-XACT etc. are also possible. Running in either interactive or batch mode, users can transform existing IP-XACT to UVM register classes or others.
IDesignSpec provides design teams a way to capture and extract register specifications within a design specification document. This methodology fits right into any system that users may already have in place. IDesignSpec can read in IP-XACT, SystemRDL, XML and CSV files with register data and generate SystemVerilog files that form input to the UVM based register verification environment.
Creating registers by hand is no fun, it as a laborious and error prone process. Use IDesignSpec to capture the specifications and the register information and generate all design and UVM based verification code from it. It is available as a plug-in for editors and spreadsheet tools (Word or Excel or OpenOffice.org) and enables users to embed register information right inside the functional specification.